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mcm69c433 ? scm69c433 1 motorola fast sram 16k x 64 cam the mcm69c433 is a flexible contentaddressable memory (cam) that can contain 16k entries of 64 bits each. the widths of the match field and the output field are programmable, and the match time is designed to be 240 ns. as a result, the mcm69c433 is well suited for datacom applications such as virtual path identifier/virtual circuit identifier (vpi/vci) translation in atm switches up to oc12 (622 mbps) data rates and media access control (mac) address lookup in ethernet/fast ethernet bridges. the match duty cycle of the mcm69c433 is userdefined, with a tradeoff between the time between the match request rate and the rate of new entries added to the cam per second. ? 16k entries ? 240 ns match time ? mask register to adon't careo selected bits ? depth expansion by cascading multiple devices ? 66 mhz maximum clock rate ? programmable match and output field widths ? concurrent matching of virtual path circuits and virtual connection circuits in atm mode ? separate ports for control and match operations ? 450 ns insertion time if 1 of 14 entry queue locations is empty ? 120 ms initialization time after fast insertion (at powerup only) ? single 3.3 v 5% supply ? ieee standard 1149.1 test port (jtag) ? 100pin tqfp package related products e mcm69c232, mcm69c432, mcm69c233 (cams) a2 a0 dq15 dq0 sel we irq dtack 14 x 64 entry queue status/ control logic input reg 16k x 64 cam table mq31 mq0 k g lh /sm ll mc ms vpc reset control port match port kmode order this document by mcm69c433/d semiconductor technical data mcm69c433 scm69c433 tq package tqfp case 983a01 rev 3 6/11/01 ? motorola, inc. 2001 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 2 motorola fast sram pin assignment 71 72 mq8 v dd mq22 69 70 66 67 68 64 65 61 62 63 37 38 34 35 36 42 43 39 40 41 45 46 44 60 59 58 57 56 55 54 53 52 51 31 32 33 74 75 76 77 78 79 80 50 49 48 47 v ss mq23 mq24 mq26 mq25 v ss mq27 v dd mq28 mq30 mq29 v dd mq7 v dd mq3 v ss mq6 mq5 mq4 v ss mq2 mq1 mq0 mq10 mq11 mq12 mq13 mq18 lh/sm dq2 dq5 dq4 dq0 dq1 a2 v ss dq3 v ss mc mq31 v ss vpc v dd g ms irq dtack tdo v dd v ss dq15 v ss v dd dq9 dq8 dq14 v ss v dd dq11 dq10 73 mq9 94 93 97 96 95 89 88 92 91 90 86 85 87 100 99 98 81 82 83 84 10 9 12 11 15 14 13 17 16 20 19 18 21 22 23 24 25 26 27 28 29 30 7 6 5 4 3 2 1 8 mq20 mq21 mq17 mq14 mq15 mq16 v dd dq13 dq12 v dd v ss dq7 a0 we sel tdi a1 v ss v dd v dd ll v ss mq19 v ss v dd v ss v dd v dd dq6 k kmode v dd trst tck tms reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 3 motorola fast sram pin descriptions pin locations symbol type description 42 44 a2 a0 input 3bit control port address bus. 58 dtack output control port data transfer acknowledge (open drain). 17 20, 23 26, 29 32, 35 38 dq15 dq0 i/o 16bit bidirectional control port data bus. 61 g input output enable control of mq31 mq0. 57 irq output control port interrupt (open drain). 39 k input interface clock, max frequency of 66 mhz. 47 kmode input see note. 89 lh /sm input latch high/start match. initiates match sequence on match data present on mq31 mq0. 92 ll input latch low. latches low order bits if match width is > 32 bits. 64 mc output match complete (open drain). 67 70, 73 76, 79 82, 85 88, 93 96, 99, 100, 1, 2, 5 8, 11 14 mq31 mq0 i/o 32bit common i/o cam data. used for input of match ram and data ram values. 62 ms output match successful (open drain). 56 reset input resets chip to a known state. 46 sel input control port chip select, active low. 52 tck input test clock, part of jtag interface. 50 tdi input test data in, part of jtag interface. 55 tdo output test data out, part of jtag interface. 51 tms input test mode select, part of jtag interface. 49 trst input tap reset part of jtag interface. 63 vpc output virtual path circuit. used in atm mode to indicate a virtual path circuit match has occurred (open drain). 45 we input control port write enable. 4, 10, 16, 22, 27, 33, 41, 48, 54, 59, 65, 71, 77, 84, 91, 97 v dd supply power supply: 3.3 v 5%. 3, 9, 15, 21, 28, 34, 40, 53, 60, 66, 72, 78, 83, 90, 98 v ss supply ground. note: assert kmode 1 clock cycle after reset is deasserted. k reset kmode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 4 motorola fast sram absolute maximum ratings (see note 1) rating symbol value unit supply voltage (see note 2) v dd 4.6 v voltage relative to v ss (see note 2) v in 0.5 to v dd + 3 v v output current per pin i out 20 ma package power dissipation (see note 3) p d e w temperature under bias (see note 3) commercial industrial t bias 10 to 85 40 to 85 c operating temperature commercial industrial t a 0 to 70 40 to 85 c storage temperature t stg 55 to 125 c notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended oper- ating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. all voltages are referenced to v ss . 3. power dissipation capability will be dependent upon package characteristics and use environment. see package thermal characteristics. dc operating conditions and characteristics (v dd = 3.3 v 5%, t j < 120 c, unless otherwise noted) recommended operating conditions (voltages referenced to v ss = 0 v) parameter symbol min typ max unit power supply voltage v dd 3.1 3.3 3.5 v operating temperature (junction) t j e e 120 c input low voltage v il 0.5* 0 0.8 v input high voltage v ih 2.2 3 5.5 v *v il (min) = 3.0 v ac (pulse width 20 ns). dc characteristics and supply currents parameter symbol min max unit active power supply current i dda e 300 ma input leakage current (0 v v in v dd ) i lkg (i) e 1 m a output leakage current (0 v v in v dd ) i lkg (o) e 1 m a output low voltage (i ol = 8 ma) v ol e 0.4 v output high voltage (i oh = 4 ma) v oh 2.4 e v package thermal characteristics rating symbol max unit thermal resistance junction to ambient (200 lfpm, 4 layer board) (see note 2) r q ja 36 c/w thermal resistance junction to board (bottom) (see note 3) r q jb 19 c/w thermal resistance junction to case (top) (see note 4) r q jc 8 c/w notes: 1. ram junction temperature is a function of onchip power dissipation, package thermal impedance, mounting site temperature, an d mounting site thermal impedance. 2. per semi g3887. 3. indicates the average thermal impedance between the die and the mounting surface. 4. indicates the average thermal impedance between the die and the case top surface. measured via the cold plate method (mil spe c883 method 1012.1). this device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this highimpedance circuit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 5 motorola fast sram capacitance (periodically sampled rather than 100% tested) parameter symbol min max unit input capacitance c in e 5 pf i/o capacitance c i/o e 8 pf junction to ambient thermal characteristics board air (lfpm) q ja ( c/w) 1 layer 0 43 1 layer 200 36 4 layer 0 33 4 layer 200 29 ac operating conditions and characteristics (v dd = 3.3 v 5%, t j < 120 c, unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 3 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output timing reference level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . output load figure 1 unless otherwise noted . . . . . . . . . . . . . . . . . . control port timings (voltages referenced to v ss = 0 v, max's are t khkh dependent and listed values are for t khkh = 15 ns) parameter symbol min max unit notes address valid to sel low t avsl 0 e ns dtack low to address invalid t dtlax 0 e ns data valid to select low t dvsl 0 e ns dtack low to data invalid t dtldx 0 e ns output valid to dtack low t qvdtl 2 e ns we valid to select low t wvsl 0 e ns dtack low to we high t dtlwh 0 e ns we high to output active t whqx 2 e ns select low to dtack low t sldtl 10 e ns 1 select high to dtack high t shdth 10 e ns dtack low to irq low t dtlil 10 e ns irq low to irq high t ilih 20 e ns dtack low to select high t dtlsh 0 e ns dtack high to select low t dthsl 0 e ns address valid to output valid t avqv e 8 ns select high to output high impedance t shqz e 8 ns reset low to reset high t rlrh 2 x t khkh e ns note: 1. dtack is delayed when a write is attempted during certain operations. see functional description. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 6 motorola fast sram match port timings (voltages referenced to v ss = 0 v, max's are t khkh dependent and listed values are for t khkh = 15 ns) parameter symbol min max unit clock cycle time t khkh 15 250 ns clock high time t khkl 6 244 ns clock low time t klkh 6 244 ns lhsm or ll low to clock high t llkh 3 e ns clock high to lhsm or ll high t khlh 1 e ns mq input data valid to clock high t mqvkh 8 e ns clock high to match data invalid t khmqx 2 e ns clock high to mq valid t khmqv e 13 ns clock high to mc high t khmch e 10 ns clock high to mc low t khmcl e 7 ns clock high to ms low t khmsl e 8 ns clock high to ms high t khmsh e 5 ns clock high to vpc low t khvpl e 8 ns clock high to vpc high t khvph e 5 ns g low to mq active t glmqx e 3.8 ns g high to mq high impedance t ghmqz e 5 ns lh /sm low to lh /sm low t smsm 22 e cycles figure 1. ac test load output z 0 = 50 w r l = 50 w v l = 1.5 v figure 2. pullup for open drain outputs mcm69c433 output pin 3.3 v fanout to load devices r h notes: 1. for irq , dtack , ms , mc , and vpc ; r h = 200 w . 2. if multiple mcm69c433s are used, r h should be placed as close to the load devices as possible. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 7 motorola fast sram functional description the mcm69c433 is a flexible contentaddressable memory (cam) that can contain 16k entries of 64 bits each. the widths of the match field and the output field are pro- grammable, and the match time is designed to be 240 ns. as a result, the mcm69c433 is well suited for datacom applications such as virtual path identifier/virtual circuit identifier (vpi/vci) translation in atm switches up to oc12 (622 mbps) data rates and media access control (mac) ad- dress lookup in ethernet/fast ethernet bridges. the match duty cycle of the mcm69c433 is determined by the user, with a tradeoff between the match request rate and the rate of entries added to/deleted from the cam. with the minimum required 60 ns of idle time between matches, a typical value of 370 insertions or deletions per second can be made. see figure 3 for a graph of the relationship between insertion/ deletion pairs and match duty cycle. in its basic operating mode, the mcm69c433 reads a data input word through mq bus and compares it to all the entries in its cam table. the mc pin is always asserted after the comparisons have been made. if a match is found, the ms pin is asserted, and the data associated with the matching entry is output on the mq bus. if no match is found, the mq bus remains in a highimpedance state to facilitate depth ex- pansion via the cascading of multiple cams. before the basic operating mode can be entered, several startup functions must be performed. first, the output width and match width must be designated by setting the globalmask register. second, a choice must be made between bufferedentry mode and fastentry mode. next, the 64bit match/output data pairs must be loaded into the table. depending on the entry mode of choice, the table may have to be initialized. optionally, the aalmost fullo point may be set to provide warning of impending table overflow. the input bits to be compared are defined by the global mask register. the mask bits that are 0 correspond to the bits that are used in the match operation.typically, the bits that are used in matching are the high order bits in the 64bit cam table entries, and the bits that are used as outputs are the low order bits. while any of the bits can be defined as match bits, the low order 32 bits of an entry are always driven on the mq bus as output data. the choice of entry mode is a tradeoff between speed of entry and latency before matching operations can begin. in a typical application, the fastentry mode will be used to load the initial values into the cam table. subsequently, the initializetable operation, which takes 120 ms, must be executed to establish the required linkages and relationships among the entries. after match operations have begun, the bufferedentry mode should be used to enter new values dynamically; even one addition in fastentry mode will dis- able matching until the table is reinitialized. table insertions using the bufferedentry mode and the fastentry mode actually take the same amount of time unless the entry queue is full. the capacity of the queue is 14 entries. after the entry mode choice is made, the table can be loaded. each 64bit entry is constructed by writing a 16bit value to each of the four i/o registers in the control port of the mcm69c433. the insertion can then be processed. after all the startup entries have been loaded into the cam table, the initialization operation is run if required. normal matching operations can then begin. a delete operation is provided to remove stale data from the cam table. several error codes are defined in the details of the instruction set. when an error occurs, its corresponding code is written into the error register and the error bit in the flag register is set. the error bit is cleared and the error register is set to ffff 16 by the next write to the operation register. programming model three types of registers are accessible through the mcm69c433's control port: i/o registers, an operation reg- ister, and result/condition code registers. each register is 16 bits in length. address register name bit number offset i/o register 0 0 i/o register 1 1 i/o register 2 2 i/o register 3 3 operation register 4 flag register 5 error code register 6 interrupt register 7 15 0 flag bit definitions bit 0: 1 = at least one interrupt enabled, 0 = no interrupts enabled bit 1: 1 = last control port match successful, 0 = last match unsuccessful bit 2: 1 = table initialized, 0 = table not initialized bit 3: 1 = bufferedentry mode, 0 = fastentry mode bit 4: 1 = entry queue empty, 0 = entry queue not empty bit 5: 1 = entry queue full, 0 = entry queue not full bit 6: 1 = cam table full, 0 = cam table not full bit 7: 1 = error condition set, 0 = no error bit 8: 1 = table almost full, 0 = table not almost full bit 9: 1 = atm mode, 0 = standard mode bit 10: 1 = last operation c omplete, 0 = not yet complete error codes ffff no error fffd invalid instruction fffc queue not empty for read fffb table not initialized fffa queue not empty for write fff9 cam table full fff8 entry queue full f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 8 motorola fast sram interrupt bit definitions bit 0: 1 = enable interrupt on insert with full entry queue bit 1: 1 = enable interrupt on insert with full table bit 2: 1 = enable interrupt on completion of checkforvalue instruction bit 3: 1 = enable interrupt on completion of initializetable instruction bit 4: 1 = enable interrupt on failed attempt to enter fastentry mode bit 5: 1 = enable interrupt on cam table reaching almostfull point bit 6: 1 = enable interrupt on fast read with nonempty queue bit 7: 1 = enable interrupt on illegal instruction instruction set details the mcm69c433 is prepared for match operations by writing data and instructions via the control port. in the gen- eral case, required data is loaded into i/o registers 0 3, then an instruction is issued by writing an operation code to the operation register. as a result of running an instruction, the cam table can be modified, bit(s) can be set in the flag register, error codes can be returned in the error code regis- ter, and an interrupt can be generated if enabled. for a par- ticular condition to generate an interrupt, the interrupt register bit specific to that condition must be set. the user should verify that the last operation complete bit (bit 10) of the flag register is set before executing the next instruction, if the instruction just executed modifies i/o registers. see the simultaneous port operations section for any exceptions. table 1. mcm69c433 operation summary operation description op code (base 16) insert value loads a new entry into the cam table 0000 or 000f delete value removes an entry from the cam table 0001 or 000e check for value runs a match cycle via the control port 0006 initialize table prepares cam table for matching 000b fastentry mode selects entry mode suited for initial cam table load 0004 bufferedentry mode selects entry mode suited for simultaneous loading and matching 0005 set atm mode enter mode that provides concurrent vpc/vcc search 0008 return entry count determines number of entries in cam 0003 set globalmask register determines match bits to be checked in a match operation 0002 or 000d set almostfull point defines cam almostfull condition 0007 set fastread register defines table entry that is output by the fastread operation 0009 fast read outputs one cam table entry 000a insert value this instruction is used to load a new match/output value into the cam. the contents of i/o registers 0 3 are con- catenated, with bit 15 of register 3 as the most significant bit, and bit 0 of register 0 as the least significant bit. if the mcm69c433 is running in the bufferedentry mode, the resulting 64bit value is written to the first available loca- tion in the entry queue, and is immediately available for matching. if a buffered insertvalue instruction is attempted when the entry queue is full (indicated by bit 5 of the flag reg- ister = 1), no value is written, an error code of fff8 16 is re- turned in the error code register, and the errorcondition flag (bit 7) is set in the flag register. an interrupt is generated, if enabled by bit 0 of the interrupt register being set. if the mcm69c433 is running in the fastentry mode, the concatenated 64bit value is written directly to the cam array. if an insertvalue instruction is attempted when in fastentry mode and the table is full, no value is written, an error code of fff9 16 is returned in the error code register, and the errorcondition flag (bit 7) is set in the flag register. (the tablefull condition is indicated by bit 6 of the flag regis- ter being set.) an interrupt is generated, if enabled by bit 1 of the interrupt register being set. only one entry is allowed for a given match pattern. if an entry is made in the table that duplicates an existing match pattern, it will overwrite the entry already in the cam table, if the cam is in bufferedentry mode. the user must ensure that no entries with the same match pattern are inserted in fastentry mode. delete value this instruction is used to remove a match/output value from the cam. the contents of i/o registers 0 3 are con- catenated, with bit 15 of register 3 as the most significant bit, and bit 0 of register 0 as the least significant bit. the bits that have a 0 in the corresponding bit of the globalmask register are used to find a matching entry in the cam table. if such an entry is found, it is invalidated. note that any bit that is not a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 9 motorola fast sram match bit as defined by the mask register is ignored for this operation. the operation of the mcm69c433 guarantees that no more than one matching entry can exist in the table, unless they were accidently loaded using fastentry mode. this must be avoided by the user, as the results of subse- quent matches and deletes will be undefined. example: i/o register 0 = 3020 16 i/o register 1 = 0000 16 i/o register 2 = 543a 16 i/o register 3 = fe55 16 concatenated value = fe55543a00003020 16 globalmask register = c0000000ffffffff 16 of the highorder 32 bits, the rightmost 30 bits are cared by the globalmask register. therefore, the mcm69c433 will delete an entry, if it exists, which has a value of 3e55543a 16 in bits 61 32. check for value this instruction checks for a matching value in the cam table via the control port. the contents of i/o registers 0 3 are concatenated, with bit 15 of register 3 as the most signifi- cant bit, and bit 0 of register 0 as the least significant bit. the bits that have a 0 in the corresponding bit of the globalmask register are used to find a matching entry in the cam table. if such an entry is found, the lastmatchsuccessful bit of the flag register is set. in addition, the matching entry is written to i/o registers 0 3, with bit 15 of register 3 as the most signifi- cant bit, and bit 0 of register 0 as the least significant bit if no match is found, the lastmatchsuccessful bit is cleared. an interrupt is generated regardless of the result, if enabled by bit 2 of the interrupt register, when the operation has been completed. the operation of the mcm69c433 guarantees that no more than one matching entry can exist in the table. if uninterrupted by match port activity, the check for value instruction will finish in 16 clock cycles. note: if both the control and matching ports are utilized simulta- neously, see the simultaneous port operations section. initialize table if fastentry mode has been used to load the cam table, the initializetable operation must be used to establish the needed relationships and linkages between the entries in the table before matching can proceed. upon completion, this operation sets the tableinitialized bit in the flag register, and generates an interrupt if enabled by bit 3 of the interrupt reg- ister. it also sets the bufferedentry mode bit in the flag regis- ter. this operation makes the programming model's registers readonly for up to 120 ms after the acknowledgment of the op code write cycle. fastentry mode this instruction is used to enter the fastentry mode. when the mcm69c433 is in this mode, insertvalue opera- tions bypass the entry queue and write new table entries directly to the cam table. the fastentry mode can only be entered while the entry queue is empty, as reflected by the queueempty flag being set (bit 4 of the flag register.) if this operation is attempted while the entry queue is not empty, the value fffa 16 is written to the error code register, the errorcondition flag (bit 7) is set in the flag register, and an interrupt is generated if enabled by bit 4 of the interrupt register. if this mode is used to enter data, the initializetable opera- tion must be executed before matching operations can begin. the entrymode bit and the tableinitialized bit of the flag register are cleared by this operation. bufferedentry mode this instruction is used to enter the bufferedentry mode. when the mcm69c433 is in this mode, insertvalue and deletevalue operations utilize the entry queue. this mode can be entered at any time. table entries are available for match operations immediately, without running the initialize table operation, if all entries are made in this mode. note that if both the bufferedentry and fastentry modes have been used to input data, none of the entries are available for matching until the initializetable operation is executed. con- flicting table and queue values are resolved in favor of the latest entry in the queue. for example, if there is an entry in the cam, a corresponding deleteentry in the queue, and a later insertentry in the queue (all with the same match data), the queued insertentry will return a match value. return entry count this operation is used to determine the number of valid en- tries in the mcm69c433. the value is returned in i/o register 0, and reflects the sum of the number of valid entries in the cam table and the inserts in the entry queue. set globalmask register this operation is used to indicate the bits to be used in per- forming matches. a 1 indicates that a bit should be ignored in the match operation, while a 0 indicates that a bit should be used in the match operation. when this operation is executed, the contents of i/o regis- ters 0 3 are concatenated, with bit 15 of register 3 as the most significant bit, and bit 0 of register 0 as the least signifi- cant bit. the resulting 64bit value is written to the global mask register. this operation should be executed before entering re- quired values into the cam table. otherwise, the initialize table instruction must be executed if the globalmask register is changed after data is loaded into the cam. set almostfull point this operation is used to define the aalmostfullo condition in the cam table. the 14 loworder bits of i/o register 0 are copied to the almostfullpoint register. if an entry is added to the mcm69c433 (via the insertvalue operation) that causes the validentry count to equal the almostfull point, then bit 8 of the flag register is set, and an interrupt is gener- ated if enabled by bit 5 of the interrupt register. the value of the almostfull register can be changed dynamically during match operations. for example, it could first be set to 8192 to generate an interrupt when the table is half full. when that point is reached, the register could be reprogrammed to 12,288 to provide warning that the table has become three quarters full. the almostfull interrupt is generated, if enabled, based on the number of entries in the cam table. entries in the queue are not included in the count. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 10 motorola fast sram set fastread register value this operation defines the table address that is output by the fastread operation. the least significant 14 bits of i/o register 0 are copied to the fastread register. the queue must be empty when this instruction is executed. fast read this operation is used to output the contents of one entry in the cam table. the fastread register is used to specify the appropriate entry, and is then autoincremented. as a re- sult, successive execution of multiple fastread operations will provide access to contiguous entries in the cam table. the cam entry is copied to i/o registers 0 3, with bit 15 of register 3 as the most significant bit, and bit 0 of register 0 as the least significant bit. the fastread instruction can only be executed while the entry queue is empty, as reflected by the queueempty flag being set (bit 4 of the flag register.) if this operation is at- tempted while the entry queue is not empty, the value fffc 16 is written to the error code register, the errorcondi- tion flag (bit 7) is set in the flag register, and an interrupt is generated if enabled by bit 7 of the interrupt register. set atm mode when the mcm69c433 is placed in atm mode, it provides simultaneous searching for virtual path circuits (vpcs) and virtual connection circuits (vccs). a vcc is detected when both the virtual path identifier (vpi) and the virtual circuit identifier (vci) of an incoming cell match an entry in the cam. a vpc match occurs when the vpi of an incoming cell matches the vpi field of a cam entry that has all 1s as its vci. a vpc match is signalled by the assertion of the vpc pin along with the ms pin. at 66 mhz, a match is completed in 240 ns, whether the applied vpi/vci belongs to a vcc or a vpc. the vci match field must be defined as bits 32 47 of each entry. the vpi match data must occupy bits 48 59. the vpi can be limited to bits 48 55, if the switch handles only usernetwork interface (uni) protocols. the mask reg- ister should be used to adon't careo any unused bits beyond the vpi field. entering atm mode will set bit 9 of the flag reg- ister. to load a vpc into the cam table, the desired vpi value is written (right justified) to i/o register 3, ffff 16 is written to i/o register 2 as the vci field, the upper half of the desired output word is written to i/o register 1, and the lower half of the desired output word is written to i/o register 0. then, the ainsert valueo instruction is written to the operation regis- ter. when performing a match operation, the vci must be placed in bits 0 15 of the mq port. the vpi is expected on bits 16 27, or bits 16 23 in the uni case. bufferedentry mode insertions and deletions are modified in the following way when the mcm69c433 is in atm mode. if you try to add a vcc with the same vpi as an existing vpc, you overwrite the vpc. if you try to delete a vcc when the vcc is not in the table, but a vpc with that vpi is in the table, the vpc will be deleted. the cam table should never contain, simultaneously, a vcc entry and vpc entry with matching vpis. violation of this requirement may lead to unpredictable behavior. bits 60 63 may be used for matching in atm mode if the application requires extra bits. the use of bits 0 31 for matching is not supported in atm mode. match duty cycle at 66 mhz, the mcm69c433 completes a match 240 ns, or 16 clock cycles, after assertion of the sm signal. how- ever, if entries need to be added to or deleted from the cam, idle time is needed between match output and match requests for control port insertions and deletions. at 66 mhz, the match duty cycle should be defined at least at 20 clock cycles (300 ns), leaving 2 clock cycles for insertions/ deletions. the additional clock cycles are used for holding the match data on the mq bus. therefore, every 20 clock cycles, when a match operation and data output are com- pleted, sm can be asserted. entries are stored from least value at the top of the table to the highest value at the bottom. if an entry with a match data value smaller than any other entry is continually added or dropped from the table, worstcase scenario occurs causing shifting of all other entries. the idle time, in terms of the num- ber cycles, needed to perform a worstcase insertion and/or deletion is given by the formula 32,768 x mdc / (mdc 18) cycles, where mdc is the match duty cycles. for example, if match requests are occurring every 20 clock cycles: 32,768 x 20 clock cycles 20 clock cycles 18 = 327,680 clock cycles at 66 mhz (15 ns per cycle) = 0.0049152 sec per insert or deletion. if both insertions and deletions are occurring = 102 insertion/deletion pairs per sec (worstcase). more typical cases consist of insertions occurring at one end of the table and deletions occurring at the other end, or when insertions and/or deletions take place toward the middle of the table. the latter scenario would consist of approximately half the total entries being shifted. the idle time, in terms of the number of cycles, needed to perform a typical insertion and/or deletion is given by the formula 16,384 x mdc / (mdc 18) cycles, where mdc is the match duty cycles. for example, if match requests are occurring every 20 clock cycles: 16,384 x 20 clock cycles 20 clock cycles 18 = 163,840 clock cycles at 66 mhz (15 ns per cycle) = 0.0024576 sec per insert or deletion. if both insertions and deletions are occurring = 203 insertion/deletion pairs per sec (typical case). the number of insertion/deletion pairs for both cases are depicted in figure 3. in general, the time for an insertion or deletion is proportional to its distance from the end of the cam table. that is, entries with the largest match value take the least time to insert or delete, while entries with the small- est values take the most time. therefore, the effective rate of f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 11 motorola fast sram figure 3. connections per second vs match cycle time match duty cycle at 66 mhz input clock 0 500 1,000 1,500 2,000 2,500 typical worst case 20 30 40 50 60 70 80 90 100 insertion deletion pairs / sec insertion and deletion is maximized if the longestlived en- tries are placed near the beginning of the table and the short- estlived entries are placed near the end of the table. for an atm application, this would correspond to the assignment of small vpi values to permanent virtual circuits and large vpi values to switched virtual circuits. note that at startup, when entries are loaded into the cam via the fastentry mode, the process is dominated by the time it takes to execute the initialization instruction that follows. the resulting effective rate of loading the cam at startup is approximately 136,500 entries per second. reset asserting reset removes all entries from the cam table and entry queue. the flag register is set to 1c 16 (setting the queue empty, bufferedentry mode, and table initialized bits). the error register is set to ffff 16 , indicating no errors. finally, the almostfull register is set to 3fff 16 . timing overview control port the control port of the mcm69c433 is asynchronous. data transfers, both read and write, are initiated by the assertion of the sel signal. address values should be valid and we should be high, when sel is asserted to begin a read cycle. all values (address, we , and sel ) should be held until the mcm69c433 asserts dtack to signal the end of the read cycle. address and data values should be valid and we should be low, when sel is asserted to begin a write cycle. address, data, we , and sel values should be held until the mcm69c433 asserts dtack to signal the end of the write cycle. match port the mcm69c433's match port is synchronous in opera- tion. when the match width is 32 bits, a match cycle can be initiated by presenting the match data on mq31 mq0 and asserting the lh /sm signal with the appropriate setup time relative to the rising edge of the clock. the assertion of the mc output signifies the completion of the match cycle. if a match has been found, the ms output is also asserted. if the match is a virtual path circuit match in atm mode, the vpc output will be asserted with the ms output. output data, if any, is enabled by the assertion of the g input. if the match width is greater than 32 bits, the lower bits are first latched into the mcm69c433 by the ll input. the match cycle is then initiated as specified in the previous paragraph. two alternative timing diagrams are presented to describe the match port timing. in the first, lh /sm must meet setup and hold specs across two consecutive clock cycles, while the mq bus need only be valid for a single cycle. in the se- cond diagram, lh /sm need only be asserted for a single clock cycle, while the mq bus must be held valid with constant data across two clock cycles. simultaneous port operations when the control and match ports are utilized simulta- neously, certain procedures must be followed. if a check for value command is issued, both the last operation complete bit (bit 10) and the entry queue empty bit (bit 4) in the flag register should be set prior to executing the check for value command in order to receive valid results. how- ever, matching on the match port can be done directly after the last operation complete flag is set. the match port has priority over the control port during simultaneous operations. depth expansion multiple cams can be cascaded to increase the depth of the match table. the hardware requirements are very straightforward, as the following pins on each device are sim- ply wired in parallel: a2 a0, dq15 dq0, we , irq , dtack , mq31 mq0, k, g , lh /sm , mc , ms , and vpc . four cams can be easily cascaded. simulations show that eight devices can be cascaded if care is taken to minimize the length of the pc board traces connecting the cams. the bufferedentry mode prevents multiple matching entries in a single cam. the check for value instruction should be used to verify that multiple matching entries will not result from a potential new entry. if a match is found in cam 1, for example, the new value should be placed in cam 1, where it will replace the existing entry. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 12 motorola fast sram depth expansion example cascading four mcm69c433s for a 64k word table a2 a0 dq31 dq0 control port match port cam 0 cam 1 cam 2 cam 3 sel0 we irq dtack sel1 sel2 sel3 mq31 mq0 k g lh /sm mc ms vpc a0 a2 dq0 dq31 we irq dtack mq0 mq31 k g lm /sm mc ms vpc a0 a2 dq0 dq31 we irq dtack mq0 mq31 k g lm /sm mc ms vpc a0 a2 dq0 dq31 we irq dtack mq0 mq31 k g lm /sm mc ms vpc a0 a2 dq0 dq31 we irq dtack mq0 mq31 k g lm /sm mc ms vpc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 13 motorola fast sram 123456 789 0 t llkh t khmsl match port timing (single clock mode 32bit match) t khlh t mqvkh note: see description of match port timing. k lhbsm g mq31 mq0 mc ms vpc 10 15 16 17 18 19 11 12 13 14 20 21 22 23 t khmch t khmsh t khvph ll t khmqv t mqvkh t khmcl t khvpl t khmch t khmsh t khvph t llkh t khlh t ghmqz d out d in 0 ns 75 ns 150 ns 225 ns 300 ns 375 ns alternate a d in t khmqx t glmqx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 14 motorola fast sram 123456 789 0 t llkh t khmsl match port timing (single clock mode 32bit match) t khlh t mqvkh note: see description of match port timing. k lhbsm g mq31 mq0 mc ms vpc 10 15 16 17 18 19 11 12 13 14 20 21 22 23 t khmqx t khmch t khmsh t khvph ll t khmqv t mqvkh t khmcl t khvpl t khmch t khmsh t khvph t llkh t khlh t ghmqz d out d in 0 ns 75 ns 150 ns 225 ns 300 ns 375 ns alternate b d in t glmqx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 15 motorola fast sram a2 a0 sel dq15 dq0 we dtack irq t dvsl t shdth t dtlil control port timing t avsl t wvsl t dtlax t dtlsh t dtldx t dtlwh t sldtl t avqv t sldtl t shqz t avsl t ilih a b data in data out t shdth t qvdtl f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 16 motorola fast sram jtag ac operating conditions and characteristics for the test access port (ieee 1149.1) (t j < 120 c, unless otherwise noted) input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 3 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output measurement timing level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . output load 50 w termination to 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . tap controller timing parameter symbol min max unit notes cycle time t ck 30 e ns clock high time t ckh 12 e ns clock low time t ckl 12 e ns clock low to output valid t a 5 9 ns clock low to output highz t ckz 0 9 ns 1 clock low to output active t ckx 0 9 ns 2, 3 setup times: tms tdi trst t s t sd t sr 2 2 2 e ns hold times: tms tdi trst t h t hd t hr 2 2 10 e ns notes: 1. tdo will highz from a clock low edge depending on the current state of the tap state machine. 2. tdo is active only in the shiftir and shiftdr state of the tap state machine. 3. transition is measured 500 mv from steadystate voltage. this parameter is sampled and not 100% tested. tdi test data in tck test clock t ck tdo test data out t h t ckx t sd t s t hd t a t ckz tms test mode select t ckh t ckl figure 4. tap controller timing t sr t hr trst f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 17 motorola fast sram test access port description instruction set a 5pin ieee standard 1149.1 test port (jtag) is in- cluded on this device. when the tap (test access port) con- troller is in the shiftir state, the instruction register is placed between tdi and tdo. in this state, the desired instruction would be serially loaded through the tdi input. trst resets the tap controller to the testlogic reset state. the tap instruction set for this device are as follows. standard instructions instruction code (binary) description bypass 1111* bypass instruction sample/preload 0010 sample and/or preload instruction extest 0000 extest instruction highz 1001 highz all output pins while bypass register is between tdi and tdo clamp 1100 clamp output pins while bypass register is between tdi and tdo * default state at powerup. sample/preload tap instruction the sample/preload tap instruction is used to allow scanning of the boundary scan register without causing inter- ference to the normal operation of the chip logic. the 62bit boundary scan register contains bits for all device signal and clock pins and associated control signals. this register is ac- cessible when the sample/preload tap instruction is loaded into the tap instruction register in the shiftir state. when the tap controller is then moved to the shift dr state, the boundary scan register is placed between tdi and tdo. this scan register can then be used prior to the extest instruction to preload the output pins with desired values so that these pins will drive the desired state when the extest instruction is loaded. as data is written into tdi, data also streams out tdo which can be used to presample the inputs and outputs. sample/preload would also be used prior to the clamp instruction to preload the values on the output pins that will be driven out when the clamp instruction is loaded. extest tap instruction the extest instruction is intended to be used in con- junction with the sample/preload instruction to assist in testing board level connectivity. normally, the sample/ preload instruction would be used to preload all output pins. the extest instruction would then be loaded. during extest, the boundary scan register is placed between tdi and tdo in the shiftdr state of the tap controller. once the extest instruction is loaded, the tap controller would then be moved to the runtest/idle state. in this state, one cycle of tck would cause the preloaded data on the output pins to be driven while the values on the input pins would be sampled. note the tck, not the clock pin (clk), is used as the clock input while clk is only sampled during extest. after one clock cycle of tck, the tap controller would then be moved to the shiftdr state where the sampled values would be shifted out of tdo (and new values would be shifted in tdi). these values would normally be compared to expected values to test for board connectivity. clamp tap instruction the clamp instruction is provided to allow the state of the signals driven from the output pins to be determined from the boundary scan register while the bypass register is selected as the serial path between tdi and tdo. the signals driven from the output pins will not change while the clamp instruction is selected. extest could also be used for this purpose, but clamp shortens the board scan path by insert- ing only the bypass register between tdi and tdo. to use clamp, the sample/preload instruction would be used first to scan in the values that will be driven on the output pins when the clamp instruction is active. highz tap instruction the highz instruction is provided to allow all the outputs to be placed in an inactive drive state (highz). during the highz instruction the bypass register is connected be- tween tdi and tdo. bypass tap instruction the bypass instruction is the default instruction loaded at power up. this instruction will place a single shift register between tdi and tdo during the shiftdr state of the tap controller. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. boundary scan register the boundary scan register is identical in length to the number of active input, output, and i/o connections on the device (not counting the tap pins). the boundary scan reg- ister, under the control of the tap controller, is loaded with the contents of the ram i/o ring when the controller is in capturedr state and then is placed between the tdi and tdo pins when the controller is moved to shiftdr state. several tap instructions can be used to activate the bound- ary scan register. the bit scan order table (table 2) describes which device pin connects to each boundary scan register location. the first column defines the bit's position in the boundary scan register. the shift register bit at g (i.e., first to be shifted out) is defined as bit 1. the second column is the name of the pin, third column is the pin number and the fourth column is the pin type (input, output, or i/o). disabling the test access port and boundary scan it is possible to use this device without utilizing the four pins used for the test access port. to circuit disable the device, tck must be tied to v ss to preclude midlevel inputs. although tdi and tms are designed in such a way that an undriven input will produce a response equivalent to the application of a logic 1, it is still advisable to tie these inputs to v dd through a 1k resistor. tdo should remain unconnected. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 18 motorola fast sram table 2. sample/preload boundary scan register bit definitions bit no. bit pin name bit pin no. 1 g 61 2 ms 62 3 vpc 63 4 mc 64 5 mq31 67 6 mq30 68 7 mq29 69 8 mq28 70 9 mq27 73 10 mq26 74 11 mq25 75 12 mq24 76 13 mq23 79 14 mq22 80 15 mq21 81 16 mq20 82 17 mq19 85 18 mq18 86 19 mq17 87 20 mq16 88 21 lh /sm 89 22 ll 92 23 mq15 93 24 mq14 94 25 mq13 95 26 mq12 96 27 mq11 99 28 mq10 100 29 mq9 1 30 mq8 2 31 mq7 5 32 mq6 6 bit no. bit pin name bit pin no. 33 mq5 7 34 mq4 8 35 mq3 11 36 mq2 12 37 mq1 13 38 mq0 14 39 dq15 17 40 dq14 18 41 dq13 19 42 dq12 20 43 dq11 23 44 dq10 24 45 dq9 25 46 dq8 26 47 dq7 29 48 dq6 30 49 dq5 31 50 dq4 32 51 dq3 35 52 dq2 36 53 dq1 37 54 dq0 38 55 k 39 56 a2 42 57 a1 43 58 a0 44 59 we 45 60 sel 46 61 reset 56 62 irq 57 63 dtack 58 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 19 motorola fast sram test access port pins tck e test clock (input) clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms e test mode select (input) the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input will produce the same result as a logic 1 input level. tdi e test data in (input) the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is deter- mined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (see figure 5). an undriven tdi pin will produce the same result as a logic 1 input level. tdo e test data out (output) output that is active depending on the state of the tap state machine (see figure 5). output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. trst e tap reset this device has a trst pin. trst is optional in ieee 1149.1. asserting the asynchronous trst places the tap controller in testlogic reset state. testlogic reset state can also be entered by holding tms high for five rising edges of tck. this type of reset does not affect the operation of the system logic. shiftdr exit1ir select irscan pauseir testlogic reset exit1dr updateir captureir shiftir exit2ir 0 runtest/ idle 1 pause 2dr exit2dr pause 1dr capturedr 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 select drscan 0 note: the value adjacent to each state transition represents the signal present at tms at the rising edge of tck. figure 5. tap controller state diagram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 20 motorola fast sram mcm scm 69c433 xx xx x motorola memory prefix mcm = commercial temp. scm = industrial temp. part number full commercial part numbers e MCM69C433TQ15 MCM69C433TQ15r full industrial part numbers e scm69c433tq15 scm69c433tq15r speed (15 = 15 ns) package (tq = tqfp) blank = trays, r = tape and reel ordering information (order by full part number) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 21 motorola fast sram tq package tqfp case 983a01 package dimensions dim min max millimeters a 1.60 a1 0.05 0.15 a2 1.35 1.45 b 0.22 0.38 b1 0.22 0.33 c 0.09 0.20 c1 0.09 0.16 d 22.00 bsc e 16.00 bsc e1 14.00 bsc e 0.65 bsc l 0.45 0.75 l1 1.00 ref l2 0.50 ref s 0.20 r1 0.08 r2 0.08 0.20 0 7 0 11 13 11 13 1 2 3 d1 20.00 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 3. datums a, b and d to be determined at datum plane h. 4. dimensions d and e to be determined at seating plane c. 5. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions d1 and b1 do include mold mismatch and are determined at datum plane h. 6. dimension b does not include dambar protrusion. dambar protrusion shall not cause the b dimension to exceed 0.45 (0.018). ab 0.20 (0.008) h e d ab 0.20 (0.008) c d ab 0.20 (0.008) c d 0.10 (0.004) c 0.25 (0.010) s 0.05 (0.002) s ab m 0.13 (0.005) d s c e/2 d/2 e e1 d1 d d1/2 e1/2 e/2 4x 2x 30 tips 2x 20 tips d b a c h 1 3 2 100 81 80 51 50 31 30 1 plating section bb c1 c b b1 ???? ???? base metal a seating plane view ab s view ab a2 a1 r1 l2 l l1 r2 gage plane x view y b b x=a, b, or d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 22 motorola fast sram notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 23 motorola fast sram notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mcm69c433 ? scm69c433 24 motorola fast sram motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represe ntation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the applicati on or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo para meters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all ope rating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under it s patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical imp lant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product cou ld create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expens es, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. how to reach us: usa / europe / locations not listed: motorola literature distribution; japan : motorola japan ltd.; sps, technical information center, p.o. box 5405, denver, colorado, 80217. 1-303-675-2140 or 1-800-441-2447 3-20-1, minami-azabu. minato-ku, tokyo 106-8573 japan. 8 1-3-3440-3569 technical information center: 1-800-521-6274 asia / pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tao po, n.t., hong kong. home page : http ://motorola.com/semiconductors / 852-26668334 mcm69c433/d ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .

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